AT24C32D
Write Operations
that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement.
During the internally self‑timed write cycle, any attempts to read from or write to the memory array will not
be processed.
Figure 7-4.ꢀWrite Cycle Timing
SCL
SDA
8
9
9
Data Word n
D0
ACK
ACK
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minimum tWR
can only be determined through
tWR
the use of an ACK Polling routine.
Stop
Start
Stop
Condition
Condition
Condition
7.5
Write Protection
The AT24C32D utilizes a hardware data protection scheme that allows the user to write‑protect the entire
memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin
is at GND or left floating.
Table 7-1.ꢀAT24C32D Write-Protect Behavior
WP Pin Voltage
Part of the Array Protected
Full Array
VCC
GND
None － Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation
prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition
has been sent will not alter or interrupt the execution of the write cycle.
If an attempt is made to write to the device while the WP pin has been asserted, the device will
acknowledge the device address, word address and data bytes, but no write cycle will occur when the
Stop condition is issued. The device will immediately be ready to accept a new read or write command.
DS20006047A-page 20
Datasheet
© 2018 Microchip Technology Inc.
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