25AA1024/25LC1024
2.6
Data Protection
2.7
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25XX1024 powers on in the following state:
• The device is in low-power Standby mode
(CS= 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
0
x
0
1
1
x
1
x
1
0 (low)
1 (high)
1
x = don’t care
© 2007 Microchip Technology Inc.
Preliminary
DS21836D-page 13
MICROCHIP [ MICROCHIP ]
