24AA65/24LC65/24C65
FIGURE 8-2:
CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1
Write command initiated at byte 0 of page 3 in the array;
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache cache
byte 0 byte 1
cache cache page 1 cache page 2
byte 7 bytes 8-15 bytes 16-23
cache page 7
bytes 56-63
• • •
• • •
3
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
4
Remaining pages in cache are written
to sequential pages in array.
Write cycle is executed after every page is written.
array row n
page 0 page 1 page 2 byte 0 byte 1
• • • byte 7 page 4 • • • page 7
array row n + 1
page 0 page 1 page 2
page 3 page 4 • • • page 7
5
Last page in cache written to page 2 in next row.
FIGURE 8-3:
CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
1
Write command initiated; 64 bytes of data
loaded into cache starting at byte 2 of page 0.
2
Last 2 bytes loaded 'roll over'
to beginning.
3
Last 2 bytes
loaded into
cache cache cache
byte 0 byte 1 byte 2
cache cache page 1 cache page 2
byte 7 bytes 8-15 bytes 16-23
cache page 7
bytes 56-63
page 0 of cache.
• • •
• • •
4
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
5
Remaining bytes in cache are
written sequentially to array.
Write cycle is executed after every page is written.
array
page 0 page 1 page 2
page 0 page 1 page 2
• • •
page 4 • • • page 7
page 4 • • • page 7
byte 0 byte 1 byte 2 byte 3 byte 4
page 3
byte 7
row n
array
row
n + 1
6
Last 3 pages in cache written to next row in array.
2003 Microchip Technology Inc.
DS21073J-page 13
MICROCHIP [ MICROCHIP ]
