24LC04B/08B
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
DATA n
S
T
O
P
SDA LINE
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
BUS ACTIVITY
MASTER
DATA (n)
S
SDA LINE
A
C
K
A
C
K
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-3:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SEQUENTIAL READ
CONTROL
BYTE
S
T
O
P
DATA n
DATA n + 1
DATA n + 2
DATA n + X
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
8.0
8.1
PIN DESCRIPTIONS
SDA Serial Address/Data Input/Output
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC04B/08B as
a serial ROM when WP is enabled (tied to V
CC
).
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10KΩ for 100 kHz, 1KΩ for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.4
A0, A1, A2
8.2
SCL Serial Clock
These pins are not used by the 24LC04B/08B. They
may be left floating or tied to either V
SS
or V
CC
.
This input is used to synchronize the data transfer from
and to the device.
©
1996 Microchip Technology Inc.
DS21051E-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
