24LC04B/08B
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
VCC = 4.5 - 5.5V
FAST MODE
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first clock
pulse is generated
START condition setup time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission can
start
Output fall time from VIH min
to VIL max
TOF
TSP
TWR
—
—
—
250
50
20 +0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
—
(Note 3)
Write cycle time
10
—
10
ms
Byte or Page mode
Endurance
24LC04B
24LC08B
25°C, Vcc = 5.0V, Block Mode
(Note 4)
—
—
10M
1M
—
—
10M
1M
—
—
cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model whcih can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
1996 Microchip Technology Inc.
DS21051E-page 3
MICROCHIP [ MICROCHIP ]
