24LC01B/02B Modules
TABLE 1-2
AC CHARACTERISTICS
Tamb = 0
°
C to +70
°
C
Remarks
All parameters apply across the specified operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted.
Commercial (C):
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
STD MODE
FAST MODE
Units
Symbol
Min.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WC
—
—
—
1M
250
50
10
—
20 +0.1
C
B
—
—
1M
250
50
10
—
ns
ns
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
100 pF
(Notes 1, 3)
ms Byte or Page mode
cycles 25
°
C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
T
R
SCL
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
HD
:
STA
T
SP
T
AA
T
BUF
SDA
OUT
©
1997 Microchip Technology Inc.
DS21222A-page 3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
