24AA02/24LC02B
4.4
Data Valid (D)
3.0
FUNCTIONAL DESCRIPTION
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The 24XX02 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XX02
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
4.5
Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Note:
The 24XX02 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
4.1
Bus Not Busy (A)
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX02) will leave the data line
high to enable the master to generate the Stop
condition.
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Stop
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
DS21709J-page 6
© 2009 Microchip Technology Inc.
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