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24LC02B-I/P 参数 Datasheet PDF下载

24LC02B-I/P图片预览
型号: 24LC02B-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 2K I2C ™串行EEPROM [2K I2C™ Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 32 页 / 583 K
品牌: MICROCHIP [ MICROCHIP ]
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24AA02/24LC02B  
TABLE 1-2:  
AC CHARACTERISTICS  
Industrial (I):  
Automotive (E):  
TA = -40°C to +85°C, VCC = +1.7V to +5.5V  
TA = -40°C to +125°C,VCC = +2.5V to +5.5V  
AC CHARACTERISTICS  
Param.  
Sym.  
No.  
Characteristic  
Clock frequency  
Min.  
Typ.  
Max.  
Units  
Conditions  
1
2
3
4
FCLK  
THIGH  
TLOW  
TR  
400  
100  
kHz 2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
2.5V VCC 5.5V  
Clock high time  
Clock low time  
600  
4000  
ns  
ns  
ns  
1.7V VCC < 2.5V (24AA02)  
1300  
4700  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
SDA and SCL rise time  
(Note 1)  
300  
1000  
2.5V VCC 5.5V (Note 1)  
1.7V VCC < 2.5V (24AA02)  
(Note 1)  
5
TF  
SDA and SCL fall time  
300  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(Note 1)  
6
THD:STA Start condition hold time  
600  
4000  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
7
TSU:STA Start condition setup  
time  
600  
4700  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
8
THD:DAT Data input hold time  
0
(Note 2)  
9
TSU:DAT Data input setup time  
100  
250  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
10  
11  
12  
TSU:STO Stop condition setup  
time  
600  
4000  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
TAA  
Output valid from clock  
(Note 2)  
900  
3500  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
TBUF  
Bus free time: Time the  
bus must be free before  
a new transmission can  
start  
1300  
4700  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
13  
14  
TOF  
TSP  
Output fall time from VIH 20+0.1CB  
250  
250  
ns  
ns  
2.5V VCC 5.5V  
1.7V VCC < 2.5V (24AA02)  
minimum to VIL  
maximum  
Input filter spike  
suppression  
50  
(Notes 1 and 3)  
(SDA and SCL pins)  
15  
16  
TWC  
Write cycle time (byte or  
page)  
5
ms  
Endurance  
1M  
cycles 25°C, (Note 4)  
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.  
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved  
noise spike suppression. This eliminates the need for a TI specification for standard operation.  
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific  
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site  
at www.microchip.com.  
© 2009 Microchip Technology Inc.  
DS21709J-page 3  
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