ML6697
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MDC-MDIO (MII Management Interface)
tSPWS
tSPWH
tSPRS
Write Setup Time, MDIO Data
Valid to MDC Rising Edge
1.4V Point
10
ns
Write Hold Time, MDIO Data
Valid After MDC Rising Edge
1.4V Point
10
100
0
ns
ns
ns
Read Setup Time, MDIO Data
Valid to MDC Rising Edge
1.4V Point
tSPRH
Read Hold Time, MDIO Data
Valid After MDC Rising Edge
1.4V Point
tCPER
tCPW
Period of MDC
400
160
ns
ns
Pulsewidth of MDC
Positive or negative pulses
Note 1.
Note 2.
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Measured using the test circuit shown in fig. 1, under the following conditions:
RLP = 200W, RLS = 49.9W, RTSET = 2.49kW.
All resistors are 1% tolerance.
Note 3.
Note 4.
Note 5.
Output current amplitude is IOUT = 40 ´ 1.25V/RTSET.
Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.
Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The
times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the
external network coupling transformer and EMI/RFI emissions filter.
Note 6.
Note 7.
Differential test load is shown in fig. 1 (see note 2).
Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The
adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to
either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.
From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI.
Note 8.
Note 9.
From first bit of J at the MDI, to CRS.
Note 10. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.
V
CC
TPOUTP
2:1
R
LP
200Ω
1
R
LP
200Ω
2
R
LS
49.9Ω
R
LS
49.9Ω
TPOUTN
Figure 1.
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
