ML6697
MII MANAGEMENT INTERFACE REGISTERS
TABLE 1: CONTROL REGISTER
BIT(s)
NAME
DESCRIPTION
R/W
DEFAULT
0.15
Reset
1 = reset all register bits to defaults
0 = normal operation
R/W, SC
0
0.14
0.13
0.11
Loopback
1 = PMD loopback mode
0 = normal operation
R/W
RO
0
1
0
0
Manual Speed Select
Power down
1 = 100Mb/s
0 = 10Mb/s
1 = power down
0 = normal operation
R/W
RO
0.12,
Not Used
0.10-0.0
TABLE 2: STATUS REGISTER
BIT(s)
NAME
DESCRIPTION
R/W
DEFAULT
1.14
100BASE-TX full duplex
1 = full duplex 100BASE-TX capability
0 = No full duplex 100BASE-TX capability
RO
0
1.13
1.2
100BASE-TX half duplex
Link status
1 = half duplex 100BASE-TX capability
0 = no half duplex 100BASE-TX capability
RO
RO/LL
RO
1
1 = 100BASE-TX line is up
0 = 100BASE-TX link is down
latch low after
link fail until read
1.0
Extended capability
Not used
1 = extended register capabilities
0 = basic register set only
0
1.15,
1.12-1.3,
1.1
RO
0
NOTE:
KEY:
All unnamed or unused register locations will return a 0 value when accessed.
LL = latch low until read, R/W = read/write, RO = read only, SC = self-clearing.
12
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
