ML6697
PIN DESCRIPTION (Pin numbers for TQFP package in parentheses)
PIN
NAME
DESCRIPTION
1
(56)
TXCLKIN
Transmit clock TTL input. This 25MHz clock is the frequency reference for the
internal transmit PLL clock multiplier. This pin should be driven by an external
25MHz clock at TTL or CMOS levels.
2
(58, 57)
AGND1
Analog ground.
3, 4
5, 6
(59,60,
61,62)
TXD<3:0>
Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data
appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of TXCLK.
7
8
9
(63)
(64)
(1)
TXEN
Transmit enable TTL input. Driving this input high indicates to the ML6697 that
transmit data are present at TXD<3:0>. TXEN edges should be synchronous with
TXCLK.
TXER
Transmit error TTL input. Driving this pin high with TXEN also high causes the part
to continuously transmit scrambled H symbols. When TXEN is low, TXER has no
effect.
TXCLK
RXD<3:0>
Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal
125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6697 on
the rising edge of this clock.
10, 12, (2, 5,
14, 16 8, 11)
Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK’s rising edge.
11
13
15
17
(3, 4)
(6, 7)
(9, 10)
(12)
DGND1
DVCC1
DGND2
RXCLK
Digital ground.
Digital +5V power supply.
Digital ground.
Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the
internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive
data at RXD<3:0> changes on the falling edges and should be sampled on the rising
edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX
signal is not present at TPINP/N.
18
19
(13)
(14)
CRS
Carrier Sense TTL output. CRS goes high in the presence of non-idle signals at TPINP/
N. CRS goes low when receive is idle.
RXEN
Receive enable TTL input. When this input is high, all the MII TTL outputs are
enabled. When this input is low, all the MII TTL outputs are in high impedance
mode. This input does not affect MDIO, TXCLK and CRS.
20
21
(15, 16)
(17)
DGND3
RXDV
Digital ground.
Receive data valid TTL output. This output goes high when the ML6697 is receiving
a data packet. RXDV should be sampled synchronously with RXCLK’s rising edge.
22
23
(18)
(19)
DVCC2
RXER
Digital +5V power supply.
Receive error TTL output. This output goes high to indicate error or invalid symbols
within a packet, or corrupted idle between packets. RXER should be sampled
synchronously with RXCLK’s rising edge.
24
(20)
MDC
MII Management Interface clock TTL input. A clock at this pin clocks serial data into
or out of the ML6697’s MII management registers through the MDIO pin. The
maximum clock frequency at MDC is 2.5MHz.
4
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
