ML2724
PIN
SIGNAL
NAME
I/O
FUNCTION
DIAGRAM
MODE CONTROL AND INTERFACE LINES
VDD
31
1
XCEN
I (CMOS)
Enables the bandgap reference and
voltage regulators when high. Consumes
only leakage current in STANDBY mode
when low. This is a CMOS input, and the
thresholds are referenced to VDD and
VSS.
XCEN
1
2
RXON
I (CMOS)
TX/RX Control Input. Switches the
transceiver between TRANSMIT and
RECEIVE modes. Circuits are
powered up and signal paths
reconfigured according to the
operating mode. This is a CMOS
input, and the thresholds are
referenced to VDD and VSS.
2
RXON
DIN
30
8
VSS
VDD
31
3
PAON
O (CMOS)
PA Control Output. Enables the off-chip
PA at the correct times in a Transmit slot.
Goes high when transmit RF is present
at TXO; goes low 5µs before transmit RF
is removed from TXO. Has interlock logic
to shut down the PA if the PLL does not
lock.
3
PAON
VSS
8
VCCA
24
9
FREF
I
Input for the 12.288 MHz or 6.144 MHz
reference frequency. This input is used
as the reference frequency for the PLL
and as a calibration frequency for the on-
chip filters. An AC-coupled sine or
square wave source drives this self-
biased input.
9
40k
FREF
40k
8
VSS
DS2724-F-01
FINAL DATASHEET
APRIL 2003
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
