ML2280, ML2283
t
1H
t
1H
t
r
V
CC
DATA
OUTPUT
90%
50%
10%
CS
R
L
GND
C
L
t
1H
V
OH
90%
DO AND
SARS OUTPUTS
GND
t
0H
t
0H
V
CC
t
r
V
CC
90%
50%
10%
CS
R
L
GND
DATA
OUTPUT
t
0H
V
V
CC
C
L
DO AND
SARS OUTPUTS
10%
OL
Figure 1. High Impedance Test Circuits and Waveforms
Data Input Timing
Data Output Timing
CLK
CLK
t
t
t
t
PD0, PD1
PD0, PD1
t
SET-UP
DATA
OUT (DO)
CS
t
SET-UP
t
SET-UP
t
HOLD
t
HOLD
DATA
IN (DI)
SE
ML2281 Start Conversion Timing
CLK
t
SET-UP
CS
START CONVERSION
DO
BIT 7
BIT 6
(MSB)
Figure 2. Timing Diagrams
6