ML2280, ML2283
PIN CONFIGURATION
ML2280
Single Differential Input
8-Pin PDIP
ML2280
Single Differential Input
8-Pin SOIC
ML2283
4-Channel MUX
14-Pin PDIP
1
2
3
4
8
7
6
5
V
1
2
3
4
8
7
6
5
V
CC
CS
+
CS
1
2
3
4
5
6
7
8
V
CC
V+
CS
CC
CLK
DO
V
CLK
DO
V
V
V
V
V
+
9
DI
IN
IN
–
–
IN
10
11
12
13
14
CLK
SARS
DO
V
CH0
CH1
CH2
CH3
DGND
IN
GND
GND
REF/2
REF/2
TOP VIEW
TOP VIEW
REF/2
AGND
TOP VIEW
PIN DESCRIPTION
NAME
FUNCTION
NAME
FUNCTION
V
Positive supply. 5V ± 10%
SARS
Successive approximation register status.
Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When CS = 1, SARS
is in high impedance state.
CC
DGND
Digital ground. 0 volts. All digital inputs and
outputs are referenced to this point.
AGND
Analog ground. The negative reference voltage
for A/D converter.
GND
CH0,
Combined analog and digital ground.
CLK
Clock. Digital input which clocks data in on
DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.
Analog inputs. Digitally selected to be single
V +, V – ended (V ) or; V + or V – of a differential
IN
IN
IN
IN
IN
input. Analog range = GND - V - V
.
IN
CC
V
Reference. The analog input range is twice the
positive reference voltage value applied to this
pin.
REF/2
DI
Data input. Digital input which contains serial
data to program the MUX and channel
assignments.
V+
Input to the Shunt Regulator.
CS
Chip select. Selects the chip for multiplexer
and channel assignment and A/D conversion.
When CS = 1, all digital outputs are in high
impedance state. When CS = 0, normal A/D
conversion takes place.
DO
Data out. Digital output which contains result
of A/D conversion. The serial data is clocked
out on falling edges of CLK.
2