WEDPN16M64V-XB2X
PRELIMINARY
TRUTH TABLE — COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION)
CS#
H
L
RAS#
CAS#
WE#
X
DQM
X
ADDR
I/Os
COMMAND INHIBIT (NOP)
X
H
L
X
H
H
L
X
X
X
NO OPERATION (NOP)
H
H
H
L
X
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
L
X
Bank/Row
X
L
H
H
H
L
L/H 8
L/H 8
X
Bank/Col
X
L
L
Bank/Col
Valid
Active
X
L
H
H
L
L
X
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
X
Code
L
L
H
L
X
X
X
L
L
L
X
Op-Code
X
Write Enable/Output Enable (8)
–
–
–
–
L
–
–
Active
High-Z
Write Inhibit/Output High-Z (8)
–
–
–
–
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register and A12 should be driven low.
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for
CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock
delay).
while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst, except
in the full-page burst mode, where AUTO PRECHARGE does
not apply. AUTO PRECHARGE is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE command.
REFRESH command will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(tRC), once every refresh period (tREF).
SELF REFRESH*
AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in
the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like anAUTO
REFRESH command except CKE is disabled (LOW). Once the
SELF REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of CKE, which
must remain LOW.
another command to the same bank until the precharge time (tRP
is completed. This is determined as if an explicit PRECHARGE
command was issued at the earliest possible time.
)
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered READ
or WRITE command prior to the BURST TERMINATE command
will be truncated.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
minimum period equal to tRAS and may remain in self refresh
mode for an indefinite period beyond that.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in
conventional DRAMs. This command is nonpersistent, so it must
be issued each time a refresh is required. All active banks must
be precharged prior to issuing an AUTO REFRESH command.
The AUTO REFRESH command should not be issued until the
minimum tRP has been met after the PRECHARGE command as
shown in the operations section.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks) for
t
XSR, because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands
must be issued as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each 256Mb SDRAM requires 8,192AUTO REFRESH
cycles every refresh period (tREF). Providing a distributed AUTO
* Self refresh available in commercial and industrial temperatures only.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 1
7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
