WEDPN16M64V-XB2X
PRELIMINARY
capability to randomly change column addresses on each clock
cycle during a burst access.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecified operation.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of anACTIVE command which
is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank, A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
FIGURE 3 – MODE REGISTER DEFINITION
A12 A11 A10
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register definition, command descriptions and device
operation.
12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
Reserved*
WB Op Mode CAS Latency BT Burst Length
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
INITIALIZATION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
2
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Once power is applied and the clock
is stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a
100μs delay prior to issuing any command other than a COMMAND
INHIBIT or a NOP. Starting at some point during this 100μs period
and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
4
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Sequential
Interleaved
1
Once the 100μs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied, a
PRECHARGE command should be applied. All banks must be
precharged, thereby placing the device in the all banks idle state.
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should be
loaded prior to applying any operational command.
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
REGISTER DEFINITION
MODE REGISTER
Standard Operation
All other states reserved
-
-
The Mode Register is used to define the specific mode of operation
of the SDRAM. This definition includes the selec-tion of a burst
length, a burst type, a CAS latency, an operating mode and a
write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
Write Burst Mode
M9
0
1
Programmed Burst Length
Single Location Access
that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Mode register bits M0-M2 specify the burst length, M3 specifies
the type of burst (sequential or interleaved), M4-M6 specify the
CAS latency, M7 and M8 specify the operating mode, M9 specifies
the WRITE burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be driven LOW
during loading of the mode register.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 1
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
