W78M32VP-XBX
FIGURE 24 – TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tAHT
tAS
Addresses
CS#
tAHT
tASO
tCSPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Valid
Status
Valid
DQ6/DQ2
RY/BY#
Valid Data
Status
Status
(first read)
(second read)
(stops toggling)
Note:
1. A = Valid address; Not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
2. CE# does not need to go high between status bit reads.
FIGURE 25 – DQ2 VS. DQ6
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
40
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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