W78M32VP-XBX
FIGURE 21 – ACCELERATED PROGRAM TIMING DIAGRAM
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
Notes:
1. Not 100% tested
2. CE#, OE# = VIL
3. OE#, = VIL
4. See figure 4 and Table 32 for test specifications
FIGURE 22 – CHIP/SECTOR ERASE OPERATION TIMINGS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
2AAh
SA
VA
VA
555h for
chip erase
tAH
CS#
OE#
tCH
tWHWH2
tWP
WE#
Data
tWPH
tCS
tDS
tDH
30h
DOUT
55h
Status
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "write operation status")
2. These wave forms are for word mode.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
38
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