W78M32VP-XBX
FIGURE 23 – DATA# POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
VA
Addresses
VA
VA
tACC
tCS
CS#
OE#
tCH
tOE
tOEH
tDF
tOH
WE#
DQ7
High Z
High Z
Valid Data
Complement
Complement
True
Status Data
True
Valid Data
Status Data
DQ6–DQ0
RY/BY#
tBUSY
Notes:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2. OE for data polling is 35ns when VIO = 2.7 to 3.6V.
T
3. CE# does not need to go high between status bit reads.
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August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
39
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