W3E32M64S-XSBX
White Electronic Designs
DENSITY COMPARISONS
TSOP Approach (mm)
Actual Size
11.9
11.9
11.9
11.9
S
A
V
I
N
G
S
W3E32M64S-XSBX
13
66
TSOP
66
TSOP
66
TSOP
66
TSOP
22.3
22
Area
4 x 265mm2 = 1060mm2
4 x 66 pins = 264 pins
286mm2
73%
21%
I/O
208 Balls
Count
Actual Size
W3E32M64S-XSBX
S
A
V
I
N
G
S
CSP Approach (mm)
10.0
10.0
10.0
10.0
13
60
FBGA
60
60
60
FBGA
12.5
FBGA
FBGA
22
2
2
2
Area
4 x 125mm = 500mm
4 x 60 balls = 240 balls
286mm
43%
13%
I/O
208 Balls
Count
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with theACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
Prior to normal operation, the DDR SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
January 2008
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
