W3E32M64S-XSBX
White Electronic Designs
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
H
L
RAS#
CAS#
WE#
X
ADDR
X
DESELECT (NOP) (9)
X
H
L
X
H
H
L
NO OPERATION (NOP) (9)
H
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
L
H
Bank/Row
Bank/Col
Bank/Col
X
L
H
H
H
L
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
Code
X
L
L
H
L
L
L
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
DM
L
DQs
WRITE ENABLE (10)
WRITE INHIBIT (10)
Valid
X
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
theAUTO REFRESH period. TheAUTO REFRESH period
begins when theAUTO REFRESH command is registered
and ends tRFC later.
The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR
,
because time is required for the completion of any internal
refresh in progress.
SELF REFRESH*
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except CKE
are “Don’t Care” during SELF REFRESH. VREF voltage is
also required for the full duration of SELF REFRESH.
* Self refresh available in commercial and industrial temperatures only.
January 2008
Rev. 6
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
