W3E32M64S-XSBX
White Electronic Designs
FIGURE 4 – CAS LATENCY
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
T0
T1
T2
T2n
T3
T3n
A
10
A
9
A8
A7
A6
A5
A4
A3
A
2
A
1
A0
BA1
BA0
A12
A
11
Address Bus
CLK
CLK
COMMAND
READ
NOP
NOP
NOP
Extended Mode
Register (Ex)
1
1
0
1
NA DLL
Operating Mode
CL = 2
DQS
DQ
E0
DLL
0
1
Enable
Disable
T0
T1
T2
T2n
T3
T3n
CLK
CLK
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
DQS
DQ
E2
0
E1, E0
Valid
-
Operating Mode
Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
-
Reserved
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
DATA
DON'T CARE
TRANSITIONING DATA
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125μs (maximum).
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
January 2008
Rev. 6
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
