欢迎访问ic37.com |
会员登录 免费注册
发布采购

W3E32M64S-266SBI 参数 Datasheet PDF下载

W3E32M64S-266SBI图片预览
型号: W3E32M64S-266SBI
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX64, 0.75ns, CMOS, PBGA208, 13 X 22 MM, PLASTIC, BGA-208]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 18 页 / 648 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
 浏览型号W3E32M64S-266SBI的Datasheet PDF文件第2页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第3页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第4页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第5页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第7页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第8页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第9页浏览型号W3E32M64S-266SBI的Datasheet PDF文件第10页  
W3E32M64S-XSBX  
White Electronic Designs  
be followed by a LOAD MODE REGISTER command to the  
mode register (BA0/BA1 both LOW) to reset the DLL.  
NO OPERATION (NOP)  
The NO OPERATION (NOP) command is used to perform  
a NOP to the selected DDR SDRAM (CS# is LOW while  
RAS#, CAS#, and WE# are high). This prevents unwanted  
commands from being registered during idle or wait states.  
Operations already in progress are not affected.  
TABLE 2 – CAS LATENCY  
ALLOWABLE OPERATING FREQUENCY (MHz)  
SPEED  
-200  
CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3  
75  
100  
100  
100  
125  
133  
166  
133  
-250  
LOAD MODE REGISTER  
-266  
The Mode Registers are loaded via inputs A0-12. The  
LOAD MODE REGISTER command can only be issued  
when all banks are idle, and a subsequent executable  
command cannot be issued until tMRD is met.  
-333 (IND)  
-333 (MIL)  
166  
166  
The extended mode register must be loaded when all  
banks are idle and no bursts are in progress, and the  
controller must wait the specified time before initiating  
any subsequent operation. Violating either of these  
requirements could result in unspecified operation.  
ACTIVE  
The ACTIVE command is used to open (or activate) a  
row in a particular bank for a subsequent access. The  
value on the BA0, BA1 inputs selects the bank, and the  
address provided on inputsA0-12 selects the row. This row  
remains active (or open) for accesses until a PRECHARGE  
command is issued to that bank. A PRECHARGE  
command must be issued before opening a different row  
in the same bank.  
OUTPUT DRIVE STRENGTH  
The normal full drive strength for all outputs are specified to  
be SSTL2, Class II. The DDR SDRAM supports an option  
for reduced drive. This option is intended for the support  
of the lighter load and/or point-to-point environments. The  
selection of the reduced drive strength will alter the DQs  
and DQSs from SSTL2, Class II drive strength to a reduced  
drive strength, which is approximately 54 percent of the  
SSTL2, Class II drive strength.  
READ  
The READ command is used to initiate a burst read access  
to an active row. The value on the BA0, BA1 inputs selects  
the bank, and the address provided on inputsA0-9 selects  
the starting column location. The value on input A10  
determines whether or notAUTO PRECHARGE is used. If  
AUTO PRECHARGE is selected, the row being accessed  
will be precharged at the end of the READ burst; if AUTO  
PRECHARGE is not selected, the row will remain open  
for subsequent accesses.  
DLL ENABLE/DISABLE  
When the part is running without the DLL enabled, device  
functionality may be altered. The DLL must be enabled for  
normal operation. DLL enable is required during power-  
up initialization and upon returning to normal operation  
after having disabled the DLL for the purpose of debug or  
evaluation. (When the device exits self refresh mode, the  
DLLis enabled automatically.)Any time the DLLis enabled,  
200 clock cycles with CKE high must occur before a READ  
command can be issued.  
WRITE  
The WRITE command is used to initiate a burst write  
access to an active row. The value on the BA0, BA1 inputs  
selects the bank, and the address provided on inputsA0-9  
selects the starting column location. The value on inputA10  
determines whether or notAUTO PRECHARGE is used. If  
AUTO PRECHARGE is selected, the row being accessed  
will be precharged at the end of the WRITE burst; ifAUTO  
PRECHARGE is not selected, the row will remain open for  
subsequent accesses. Input data appearing on the D/Qs  
is written to the memory array subject to the DQM input  
logic level appearing coincident with the data. If a given  
DQM signal is registered LOW, the corresponding data  
will be written to memory; if the DQM signal is registered  
COMMANDS  
The Truth Table provides a quick reference of available  
commands. This is followed by a written description of  
each command.  
DESELECT  
The DESELECT function (CS# High) prevents new  
commands from being executed by the DDR SDRAM. The  
SDRAM is effectively deselected. Operations already in  
progress are not affected.  
January 2008  
Rev. 6  
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com