W3E32M64S-XSBX
White Electronic Designs
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
After CKE passes through VIH, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable command.
WE
0
RAS
CAS
0
0
WE RAS CAS
REF
V
REF
V
A
0-12
A0-12
DQ
0
DQ
0
BA0-1
CLK
BA0-1
=
Y
=
Y
CLK
0
=
Y
=
Y
CLK
CKE
0
0
0
0
0
0
0
CLK
=
Y
=
Y
U0
CKE
=
Y
=
Y
CS
CS
=
Y
=
Y
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ15
WE1
RAS
CAS
1
1
WE RAS
CAS
V
REF
A
0-12
DQ
0
DQ16
BA0-1
CLK
CLK
=
Y
=
Y
CLK
1
=
Y
=
Y
CLK
CKE
1
1
1
1
1
1
1
=
Y
=
Y
U1
CKE
=
Y
=
Y
=
Y
CS
CS
=
Y
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ31
WE2
RAS
CAS
2
2
WE RAS
CAS
V
REF
A
0-12
DQ
0
DQ32
BA0-1
CLK
=
Y
=
Y
CLK
2
2
=
Y
=
Y
CLK
CLK
=
Y
=
Y
U2
CKE
CS
2
2
2
2
CKE
=
Y
=
Y
=
Y
CS
=
Y
=
Y
=
Y
DQML
DQMH
DQML
DQMH
DQSL
DQSH
DQ15
DQ47
DQSL
DQSH
2
2
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.)Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
WE3
RAS
CAS
3
3
WE RAS
CAS
V
REF
A
0-12
DQ
0
DQ48
BA0-1
CLK
CLK
=
Y
=
Y
CLK
3
=
Y
=
Y
CLK
CKE
3
3
3
3
3
3
3
=
Y
=
Y
U3
=
Y
CKE
=
Y
=
Y
=
Y
CS
CS
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ63
January 2008
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
