15.5 Mode Change on /SS-pin
If SPEN=1, SSIG=0, MSTR=1 and /SS pin=1, the SPI is enabled in master mode. In this case, another master
can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus contention,
the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be
an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an
SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a slave select
and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will
stay in slave mode.
15.6 Write Collision
The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for
transmission can not be written to the shift register until the previous transaction is complete. The WCOL
(SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case,
the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the
collision, will be lost.
While write collision is detected for both a master or a slave, it is uncommon for a master because the master has
full control of the transfer in progress. The slave, however, has no control over when the master will initiate a
transfer and therefore collision can occur.
For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to
accept a second character. However, the received character must be read from the Data Register (SPDAT)
before the next character has been completely shifted in. Otherwise. the previous data is lost.
WCOL can be cleared in software by writing ‘1’ to the bit.
15.7 SPI Clock Rate Select
The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCTL register, as shown in
Table 15-2.
Table 15-2. SPI Serial Clock Rates
SPR1
SPR0
SPI Clock Rate @ Fosc=12MHz
Fosc divided by
0
0
1
1
0
1
0
1
3 MHz
4
750 KHz
16
187.5 KHz
93.75 KHz
64
128
Where, Fosc is the system clock.
MEGAWIN
MPC82G516A Data Sheet
78
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
