15 Serial Peripheral Interface (SPI)
The MPC82G516A provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex,
high-speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up
to 3 Mbps can be supported in either Master or Slave mode under a 12MHz system clock. It has a Transfer
Completion Flag (SPIF) and Write Collision Flag (WCOL) in the SPI status register (SPSTAT).
Figure 15-1. SPI Block Diagram
The SPI interface has four pins: MISO (P1.6), MOSI (P1.5), SPICLK (P1.7) and /SS (P1.4):
• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master
to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the MISO pin (Master In /
Slave Out). The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal I/O pins.
• /SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select
one SPI device as the current slave. An SPI slave device uses its /SS pin to determine whether it is selected. The
/SS is ignored if any of the following conditions are true:
- If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value).
- If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P1.4 (/SS) is configured as an output.
- If the /SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions.
Note that even if the SPI is configured as a master (MSTR=1), it can still be converted to a slave by driving the
/SS pin low (if SSIG=0). Should this happen, the SPIF bit (SPSTAT.7) will be set. (See Section 15.5: Mode
change on /SS-pin)
The following special function registers are related to the SPI operation:
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MPC82G516A Data Sheet
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