5.2 Data Memory
Figure 5-2 shows the internal and external data memory spaces available to the MPC82G516A user. Internal
data memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the
upper 128 bytes of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8-bit wide,
which implies an address space of only 256 bytes. Direct addresses higher than 7FH access the SFR space; and
indirect addresses higher than 7FH access the upper 128 bytes of RAM. Thus the SFR space and the upper 128
bytes of RAM occupy the same block of addresses, 80H through FFH, although they are physically separate
entities.
The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Figure 5-3. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in
the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes
above the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a
wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128 can
only be accessed by indirect addressing.
Figure 5-4 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers,
peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR
space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
To access the external data memory, the EXTRAM bit should be set to 1. Accesses to external data memory can
use either a 16-bit address (using ‘MOVX @DPTR’) or an 8-bit address (using ‘MOVX @Ri’), as described below.
Accessing by an 8-bit address
8-bit addresses are often used in conjunction with one or more other I/O lines to page the RAM. If an 8-bit
address is being used, the contents of the Port 2 SFR remain at the Port 2 pins throughout the external
memory cycle. This will facilitate paging access. Figure 5-5 shows an example of a hardware configuration for
accessing up to 2K bytes of external RAM. Port 0 serves as a multiplexed address/data bus to the RAM, and
3 lines of Port 2 are being used to page the RAM. The CPU generates /RD and /WR (alternate functions of
P3.7 and P3.6) to strobe the memory. Of course, the user may use any other I/O lines instead of P2 to page
the RAM.
Accessing by a 16-bit address
16-bit addresses are often used to access up to 64k bytes of external data memory. Figure 5-6 shows the
hardware configuration for accessing 64K bytes of external RAM. Whenever a 16-bit address is used, in
addition to the functioning of P0, /RD and /WR, the high byte of the address comes out on Port 2 and it is held
during the read or write cycle.
In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. ALE (Address Latch
Enable) should be used to capture the address byte into an external latch. The address byte is valid at the
negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before /WR is
activated, and remains there until after /WR is deactivated. In a read cycle, the incoming byte is accepted at Port
0 just before the read strobe is deactivated. During any access to external memory, the CPU writes 0FFH to the
Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0 SFR may have
been holding. Note that in the MPC82G516A, there is no dedicated pin for ALE signal. The ALE becomes an
alternate function of P3.5 or P4.1, which can be selected by control bits P35ALE and P41ALE in the AUXR
register.
To access the on-chip expanded RAM (XRAM), the EXTRAM bit should be cleared to 0. Refer to Figure 5-2, the
1024 bytes of XRAM (0000H to 03FFH) are indirectly accessed by move external instruction, MOVX. An access
to XRAM will have not any outputting of address, address latch enable and read/write strobe. That means P0, P2,
P3.5/P4.1(ALE), P3.6 (/WR) and P3.7 (/RD) will keep unchanged during access of XRAM.
19
MPC82G516A Data Sheet
MEGAWIN
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