MX29LV800C T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit;see toggle
bit, DATA# polling, timing waveform)
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA# polling and toggle bit checking after auto-
FIGURE 6. AUTOMATIC CHIP ERASETIMINGWAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
tWC
tAS
VA
VA
2AAh
555h
Address
CE#
tAH
tCH
tGHWL
OE#
WE#
tWHWH2
tWP
tCS
tWPH
tDS tDH
In
Progress
55h
10h
Complete
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1183
REV. 1.4, APR. 24, 2006
33
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