MX29LV400T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A12 to A17 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
tWC
tAS
VA
VA
2AAh
SA
Address
tAH
CE
tCH
tGHWL
OE
tWHWH2
tWP
WE
tCS
tWPH
tDS tDH
In
Progress
55h
30h
Complete
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0710
REV. 1.4, NOV. 23, 2001
31
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