欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX29LV640MLTC-90 参数 Datasheet PDF下载

MX29LV640MLTC-90图片预览
型号: MX29LV640MLTC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 64M - BIT单电压3V ONLY制服行业的FLASH MEMORY [64M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 70 页 / 540 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX29LV640MLTC-90的Datasheet PDF文件第15页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第16页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第17页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第18页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第20页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第21页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第22页浏览型号MX29LV640MLTC-90的Datasheet PDF文件第23页  
MX29LV64xM H/L  
Legend:  
X=Don't care  
PD=Data to be programmed at location PA. Data is  
latched on the rising edge of WE# or CE# pulse.  
SA=Address of the sector to be erase or verified (in  
autoselect mode).  
Address bits A21-A12 uniquely select any sector.  
WBL=Write Buffer Location. Address must be within the  
same write buffer page as PA.  
RA=Address of the memory location to be read.  
RD=Data read from location RA during read operation.  
PA=Address of the memory location to be programmed.  
Addresses are latched on the falling edge of the WE# or  
CE# pulse, whichever happen later.  
DDI=Data of device identifier  
C2H for manufacture code  
WC=Word Count. Number of write buffer locations to load  
minus 1.  
BC=Byte Count. Number of write buffer locations to load  
minus 1.  
Notes:  
1. See Table 1 for descriptions of bus operations.  
2. All values are in hexadecimal.  
3. Except when reading array or automatic select data, all bus cycles are write operation.  
4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.  
5. No unlock or command cycles required when device is in read mode.  
6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if  
Q5 goes high.  
7. The fourth cycle of the automatic select command sequence is a read cycle.  
8. The device ID must be read in three cycles.The data is 01h for top boot and 00h for bottom boot.  
9. If WP# protects the highest address sectors, the data is 98h for factory locked and 18h for not factory locked. If  
WP# protects the lowest address sectors, the data is 88h for factory locked and 08h for not factor locked.  
10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.  
11. The total number of cycles in the command sequence is determined by the number of words written to the write  
buffer.The maximum number of cycles in the command sequence is 21(Word Mode) / 37(Byte Mode).  
12. Command sequence resets device for next command after aborted write-to-buffer operation.  
13. The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in  
the erase Suspend mode.The Erase Suspend command is valid only during a sector erase operation.  
14. The Erase Resume command is valid only during the Erase Suspend mode.  
15. Command is valid when device is ready to read array data or when device is in automatic select mode.  
P/N:PM1093  
REV. 1.1, AUG. 11, 2005  
19  
 复制成功!