MX25L4006E
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
8-PIN SOP (150/200mil)
PIN DESCRIPTION
8-PIN PDIP (300mil)
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O) / Serial Data
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O) / Serial
Data Output (for Dual Output mode)
1
2
3
4
VCC
CS#
SO/SIO1
WP#
8
7
6
5
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
VCC
8
7
6
5
HOLD#
SCLK
HOLD#
SCLK
SO/SIO1
GND
SI/SIO0
SI/SIO0
GND
SCLK Clock Input
WP# Write Protection
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
HOLD#
VCC
8-LAND, WSON (6x5mm)
8-LAND USON (2x3mm)
GND Ground
1
2
3
4
VCC
CS#
SO/SIO1
WP#
1
2
3
4
VCC
8
7
6
5
CS#
SO/SIO1
WP#
8
7
6
5
HOLD#
SCLK
HOLD#
SCLK
SI/SIO0
GND
SI/SIO0
GND
P/N: PM1576
REV. 1.3, FEB. 10, 2012
5
Macronix [ MACRONIX INTERNATIONAL ]
