MX25L4006E
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.
- Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from
data change.
Table 2. Protected Area Sizes
Status bit
Protect level
4Mb
BP2
0
BP1
0
BP0
0
1
0
1
0 (none)
1 (1 block)
2 (2 blocks)
3 (4 blocks)
4 (8 blocks)
5 (All)
None
Block 7
Block 6-7
Block 4-7
All
0
0
0
1
0
1
1
0
0
1
1
0
All
1
1
0
6 (All)
All
1
1
1
7 (All)
All
P/N: PM1576
REV. 1.3, FEB. 10, 2012
9
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