MX25L12845E
(11) 2 x I/O Double Transfer Rate Read Mode (2DTRD)
The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The ad-
dress (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on dual
I/O pins) shift out on both rising and falling edge of SCLK at a maximum frequency fT2. The 4-bit address can be
latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock,
the other two bits at falling edge of clock. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest ad-
dress has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as
4-bit instead of previous 1-bit.
The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks on SIO1 & SIO0 → data out inter-
leave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during data out (see
Figure 21 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address(interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall-
ing edge of clock. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruc-
tion, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → 8 dummy clocks → data out interleave on
SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data
out (see Figure 24 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).
Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is: CS# goes
low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit
per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#
goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (see Figure 25 for 4x I/
O Double Transfer Rate read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1428
REV. 0.06, MAR. 05, 2009
21
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