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MAX9124EUE 参数 Datasheet PDF下载

MAX9124EUE图片预览
型号: MAX9124EUE
PDF下载: 下载PDF文件 查看货源
内容描述: 四路LVDS线路驱动器 [Quad LVDS Line Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 9 页 / 197 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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Quad LVDS Line Driver  
Detailed Description  
Table 1. Input/Output Function Table  
The LVDS interface standard is a signaling method  
intended for point-to-point communication over a con-  
trolled-impedance medium as defined by the  
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The  
LVDS standard uses a lower voltage swing than other  
common communication standards, achieving higher  
data rates with reduced power consumption while  
reducing EMI emissions and system susceptibility to  
noise.  
ENABLES  
EN  
INPUTS  
OUTPUTS  
EN  
IN_  
X
OUT_+  
OUT_ -  
L
H
Z
L
Z
H
L
L
All other combinations  
of ENABLE inputs  
H
H
close to the device as possible, with the smaller valued  
capacitor closest to V  
.
CC  
The MAX9124 is an 800Mbps quad differential LVDS  
driver that is designed for high-speed, point-to-point,  
and low-power applications. This device accepts  
LVTTL/LVCMOS input levels and translates them to  
LVDS output signals.  
Differential Traces  
Output trace characteristics affect the performance of  
the MAX9124. Use controlled-impedance traces to  
match trace impedance to the transmission medium.  
Eliminate reflections and ensure that noise couples as  
common mode by running the differential trace pairs  
close together. Reduce skew by matching the electrical  
length of the traces. Excessive skew can result in a  
degradation of magnetic field cancellation.  
The MAX9124 generates a 2.5mA to 4.0mA output cur-  
rent using a current-steering configuration. This current-  
steering approach induces less ground bounce and no  
shoot-through current, enhancing noise margin and sys-  
tem speed performance. The driver outputs are short-  
circuit current limited and enter a high-impedance state  
when the device is not powered or is disabled.  
Maintain the distance between the differential traces to  
avoid discontinuities in differential impedance. Avoid  
90° turns and minimize the number of vias to further  
prevent impedance discontinuities.  
The current-steering architecture of the MAX9124  
requires a resistive load to terminate the signal and  
complete the transmission loop. Because the device  
switches current and not voltage, the actual output volt-  
age swing is determined by the value of the termination  
resistor at the input of an LVDS receiver. Logic states  
are determined by the direction of current flow through  
the termination resistor. With a typical 3.7mA output  
current, the MAX9124 produces an output voltage of  
370mV when driving a 100load.  
Cables and Connectors  
Transmission media should have a nominal differential  
impedance of 100. To minimize impedance disconti-  
nuities, use cables and connectors that have matched  
differential impedance.  
Avoid the use of unbalanced cables such as ribbon or  
simple coaxial cable. Balanced cables, such as twisted  
pair, offer superior signal quality and tend to generate  
less EMI due to canceling effects. Balanced cables  
tend to pick up noise as common mode, which is  
rejected by the LVDS receiver.  
Termination  
Because the MAX9124 is a current-steering device, no  
output voltage will be generated without a termination  
resistor. The termination resistors should match the dif-  
ferential impedance of the transmission line. Output  
voltage levels depend upon the value of the termination  
resistor. The MAX9124 is optimized for point-to-point  
interface with 100termination resistors at the receiver  
inputs. Termination resistance values may range  
between 90and 132, depending on the characteris-  
tic impedance of the transmission medium.  
Board Layout  
For LVDS applications, a four-layer PC board that pro-  
vides separate power, ground, LVDS signals, and input  
signals is recommended. Isolate the LVTTL/LVCMOS  
and LVDS signals from each other to prevent coupling.  
Chip Information  
TRANSISTOR COUNT: 2007  
Applications Information  
PROCESS: CMOS  
Power-Supply Bypassing  
with high-frequency, surface-mount  
Bypass V  
CC  
ceramic 0.1µF and 0.001µF capacitors in parallel as  
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