Microprocessor Supervisory Circuit
MAX791
25µs MIN
10
150mV
4.65V
LOWLINE
MR
7.5µs TYP
5
V
CC
3
BATT ON
RESET
2
1
VBATT
CHIP-ENABLE
OUTPUT
CONTROL
V
OUT
CE IN
0V
CE OUT
15µs TYP
Figure 2. Manual-Reset Timing Diagram
13
CE IN V
OUT
12
CE OUT
MR
9
RESET
GENERATION
TIMEBASE FOR
RESET AND
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
15
RESET
MANUAL RESET
MR
8
SWT
16
WDPO
*
14
6
WDO
WDI
PFI
11
7
OTHER
RESET
SOURCES
MAX791
*
PFO
1.25V
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
MAX791
4
GND
Figure 1. Block Diagram
Figure 3. Diode "OR" connections allow multiple reset sources
–—
–
to connect to MR.
_______________Detailed Description
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator or test technician to initiate a
reset. The Manual Reset Input (MR) can be connected
directly to a switch, without an external pull-up resistor
or debouncing network. It connects to a 1.25V com-
parator, and has a pull-up to V
OUT
as shown in Figure
1. The propagation delay from asserting MR to RESET
asserted is 4µs typical. Pulsing MR low for a minimum
of 15µs resets all the internal counters, sets the
Watchdog Output (WDO) and Watchdog-Pulse Output
8
(WDPO) high, and sets the Set Watchdog-Timeout
(SWT) input to V
OUT
- 0.6V, if it is not already connect-
ed to V
OUT
(for internal timeouts). It also disables the
chip-enable function, setting the Chip-Enable Output
(CE OUT) to a high state. The RESET output remains
active as long as MR is held low, and the reset-timeout
period begins after MR returns high (Figure 2).
Use this input as either a digital-logic input or a second
low-line comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
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