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MAX504CPD 参数 Datasheet PDF下载

MAX504CPD图片预览
型号: MAX504CPD
PDF下载: 下载PDF文件 查看货源
内容描述: 5V ,低功耗,电压输出,串行10位DAC [5V, Low-Power, Voltage-Output, Serial 10-Bit DACs]
分类和应用:
文件页数/大小: 16 页 / 176 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,  
S e ria l 1 0 -Bit DACs  
04/MAX15  
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)  
(V = 5V, V = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX504), C  
= 33µF (MAX504),  
DD  
SS  
REFOUT  
R = 10k, C = 100pF, T = T  
to T , unless otherwise noted.)  
MAX  
L
L
A
MIN  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
REFERENCE OUTPUT (REFOUT—MAX504 Only)  
T
= +25°C  
2.024  
2.015  
2.011  
2.048  
2.072  
2.081  
2.085  
A
Reference Output Voltage  
MAX504C  
V
MAX504E  
Temperature Coefficient  
Resistance  
TC  
30  
ppm/°C  
REFOUT  
R
(Note 4)  
0.5  
2
REFOUT  
Power-Supply Rejection Ratio  
Noise Voltage  
PSRR  
4.5V V 5.5V  
200  
400  
µV/V  
µVp-p  
µF  
DD  
e
0.1Hz to 10kHz  
n
Required External Capacitor  
C
3.3  
2.4  
REFOUT  
DIGITAL INPUTS (DIN, SCLK, CS, CLR)  
Input High  
V
IH  
V
V
Input Low  
V
IL  
0.8  
±1  
Input Current  
I
IN  
V
IN  
= 0V or V  
DD  
µA  
pF  
Input Capacitance  
DIGITAL OUTPUT (DOUT)  
Output High  
C
8
IN  
V
OH  
I
= 2mA  
V
- 1  
V
V
SOURCE  
DD  
Output Low  
V
OL  
I
= 2mA  
0.4  
SINK  
DYNAMIC PERFORMANCE  
Voltage-Output Slew Rate  
Voltage-Output Settling Time  
Digital Feedthrough  
SR  
T
= +25°C  
0.15  
0.25  
25  
5
V/µs  
µs  
A
To ±1/2LSB, VOUT = 2V  
nV-s  
CS = V , DIN = 100kHz  
DD  
REFIN = 1kHz, 2Vp-p (G = 1 or 2),  
code = 1111...  
Signal-to-Noise Plus Distortion  
SINAD  
68  
dB  
POWER SUPPLY  
Positive Supply Voltage  
V
4.5  
5.5  
400  
300  
V
DD  
MAX504  
MAX515  
260  
140  
All inputs = 0V or V  
output = no load  
,
DD  
Power-Supply Current  
I
DD  
µA  
SWITCHING CHARACTERISTICS (Note 5)  
CS Setup Time  
t
20  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CSS  
t
t
SCLK Fall to CS Fall Hold Time  
SCLK Fall to CS Rise Hold Time  
SCLK High Width  
CSH0  
CSH1  
t
35  
35  
45  
0
CH  
SCLK Low Width  
t
CL  
DS  
DH  
DO  
DIN Setup Time  
t
DIN Hold Time  
t
DOUT Valid Propagation Delay  
CS High Pulse Width  
CLR Pulse Width  
t
C
= 50pF  
80  
L
t
20  
25  
50  
CSW  
t
CLR  
t
CS Rise to SCLK Rise Setup Time  
CS1  
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