SPI/Microwire-Compatible
UART in QSOP-16
MAX3100
MAX3100 Operations
Write Operations
Table 1 shows write-configuration data. A 16-bit
SPI/Microwire write configuration clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers.
RTS
and
CTS
remain unchanged. The new
configuration is valid on
CS’s
rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed, the regis-
ters are updated when the transmission is over (T = 0).
The write-configuration bits (FEN, SHDNi, IR, ST, PE, L,
B3–B0) take effect after the current transmission is
over. The mask bits (TM,
RM, PM, RAM)
take effect
immediately after the 16th clock’s rising edge at SCLK.
MAX3100. The device enters test mode if bit 0 = 1. In
this mode, if
CS
= 0, the
RTS
pin acts as the 16x clock
generator’s output. This may be useful for direct baud-
rate generation (in this mode, TX and RX are in digital
loopback).
Normally, the write-data register loads the TX-buffer
register. To change the
RTS
pin’s state without writing
data, set the
TE
bit. Setting the
TE
bit high inhibits the
write command (Table 3).
Reading data clears the R bit and interrupt
IRQ
(Table 4).
Register Functions
Table 5 shows read/write operation and power-on reset
state (POR), and describes each bit used in program-
ming the MAX3100. Figure 5 shows parity and word-
length control.
Read Operations
Table 2 shows read-configuration data. This register
reads back the last configuration written to the
Table 1. Write Configuration (D15, D14 = 1, 1)
BIT
DIN
DOUT
15
1
R
14
1
T
13
FEN
0
12
SHDNi
0
11
TM
0
10
RM
0
9
PM
0
8
RAM
0
7
IR
0
6
ST
0
5
PE
0
4
L
0
3
B3
0
2
B2
0
1
B1
0
0
B0
0
Table 2. Read Configuration (D15, D14 = 0, 1)
BIT
DIN
DOUT
15
0
R
14
1
T
13
0
FEN
12
0
SHDNo
11
0
TM
10
0
RM
9
0
PM
8
0
RAM
7
0
IR
6
0
ST
5
0
PE
4
0
L
3
0
B3
2
0
B2
1
0
B1
0
TEST
B0
Table 3. Write Data (D15, D14 = 1, 0)
BIT
DIN
DOUT
15
1
R
14
0
T
13
0
0
12
0
0
11
0
0
10
TE
RA/FE
9
RTS
CTS
8
Pt
Pr
7
D7t
D7r
6
D6t
D6r
5
D5t
D5r
4
D4t
D4r
3
D3t
D3r
2
D2t
D2r
1
D1t
D1r
0
D0t
D0r
Table 4. Read Data (D15, D14 = 0, 0)
BIT
DIN
DOUT
15
0
R
14
0
T
13
0
0
12
0
0
11
0
0
10
0
RA/FE
9
0
CTS
8
0
Pr
7
0
D7r
6
0
D6r
5
0
D5r
4
0
D4r
3
0
D3r
2
0
D2r
1
0
D1r
0
0
D0r
8
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
