+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs in QS OP -1 6
+3V
+3V
1µF
16
15
14
13
12
11
10
9
SCK
1
2
3
4
5
6
7
8
V
DD
SCLK
CS
0.1µF
PCS0
CH0
MC683XX
MAX1248
MAX1249
CH1
DIN
MOSI
ANALOG
INPUTS
CH2
SSTRB
DOUT
MISO
CH3
COM
SHDN
VREF
DGND
AGND
REFADJ
(GND)
+2.5V
8/MAX1249
CLOCK CONNECTIONS NOT SHOWN
0.1µF
Figure 19. MAX1248/MAX1249 QSPI Connections External Reference
TMS 3 2 0 LC3 x In t e rfa c e
Figure 20 shows an application circuit to interface the
MAX1248/MAX1249 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 21.
XF
CLKX
CLKR
DX
CS
Use the following steps to initiate a conversion in the
MAX1248/MAX1249 and to read the results:
SCLK
TMS320LC3x
1) The TMS320 s hould b e c onfig ure d with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX1248/MAX1249’s SCLK
input.
MAX1249
DIN
DR
DOUT
SSTRB
2) The MAX1248/MAX1249’s CS pin is driven low by
the TMS320’s XF_ I/O port, to enable data to be
clocked into the MAX1248/MAX1249’s DIN.
FSR
3) An 8-bit word (1XXXXX11) should be written to the
MAX1248/MAX1249 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10 + 2-bit conversion result followed by
four trailing bits, which should be ignored.
4) The MAX1248/MAX1249’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1248/MAX1249.
6) Pull CS high to disable the MAX1248/MAX1249 until
the next conversion is initiated.
20 ______________________________________________________________________________________