+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs in QS OP -1 6
8/MAX1249
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Positive
Zero
Negative
Full Scale
Full Scale
Zero Scale
COM
Full Scale
Scale
VREF / 2
+ COM
-VREF / 2
+ COM
VREF + COM
COM
OUTPUT CODE
VREF
2
FS
=
+ COM
011 . . . 111
011 . . . 110
SUPPLIES
ZS = COM
-VREF
2
-FS =
+ COM
VREF
+3V
+3V
GND
000 . . . 010
000 . . . 001
000 . . . 000
1LSB =
1024
R* = 10Ω
111 . . . 111
111 . . . 110
111 . . . 101
V
DD
AGND
COM DGND
+3V DGND
100 . . . 001
100 . . . 000
DIGITAL
CIRCUITRY
MAX1248
MAX1249
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
* OPTIONAL
*COM ≥ VREF / 2
Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM,
Full Scale (FS) = VREF / 2 + COM
Figure 18. Power-Supply Grounding Connection
High-frequency noise in the V
power supply may
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
DD
affect the ADC’s high-speed comparator. Bypass the
supply to the star ground with 0.1µF and 1µF capaci-
tors close to pin 1 of the MAX1248/MAX1249. Minimize
capacitor lead lengths for best supply-noise rejection.
If the +3V power supply is very noisy, a 10Ω resistor
can be connected as a lowpass filter (Figure 18).
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest noise
operation, the ground return to the star ground’s power
supply should be low impedance and as short as pos-
sible.
Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I
The MAX1248/MAX1249 can interface with QSPI using
the circuit in Figure 19 (f
= 2.0MHz, CPOL = 0,
SCLK
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the four channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own micro-sequencer.
The MAX1248/MAX1249 are QSPI compatible up to their
maximum external clock frequency of 2MHz.
______________________________________________________________________________________ 19
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
