DS2154
PIN
NAME
FUNCTION
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high
when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5µs.
Receive Carrier Loss. Set high when the line interface detects a loss of carrier. Note: A
test mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in
place of detection at RTIP and RRING.
6
RCL
Receive Signaling Freeze. Set high when the signaling data is frozen via either
automatic or manual intervention. Used to alert downstream equipment of the condition.
8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at
the RCLK pin.
93
3
RSIGF
8MCLK
RPOSO
RNEGO
RCLKO
Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RPOSI.
91
90
89
Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output. Buffered recovered clock from the E1 line. This pin is normally
tied to RCLKI.
Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input. Clock used to clock data through the receive side framer. This pin
is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC
pin high. RCLKI must be present for the parallel control port to operate properly.
86
87
88
RPOSI
RNEGI
RCLKI
2.3 Parallel Control Port Pins
PIN
NAME
FUNCTION
Interrupt. Flags host controller during conditions and change of conditions defined in
the Status Registers 1 and 2. Active-low, open-drain output.
25
INT
Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel
control port). Set low for normal operation. Useful in board-level testing.
Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select
multiplexed bus operation.
14
55
TEST
MUX
Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as
the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
D0–D7/
56–65
66–72
11
AD0–AD7
Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus
timing. This pin controls the function of the RD ( DS), ALE(AS), and WR (R/ W ) pins.
If BTS = 1, then these pins assume the function listed in parentheses.
A0–A6
BTS
Read Input (Data Strobe). RD and DS are active-low signals when MUX = 1. DS is
74
75
RD(DS)
active high when MUX = 0. See the bus timing diagrams.
CS
Chip Select. Must be low to read or write to the device. CS is an active-low signal.
A7 or Address Latch Enable (Address Strobe). In nonmultiplexed bus operation
(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),
serves to demultiplex the bus on a positive-going edge.
73
77
ALE(AS)
WR(R/W)
Write Input (Read/Write). WR is an active-low signal.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
