DS2154
PIN
NAME
FUNCTION
Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the
LIUC pin high.
38
TPOSI
Transmit Negative Data Input. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TNEGO by tying the
LIUC pin high.
Transmit Clock Input. Line interface transmit clock. Can be internally connected to
TCLKO by tying the LIUC pin high.
39
40
TNEGI
TCLKI
2.2 Receive Side Digital Pins
PIN
NAME
FUNCTION
Receive Link Data. Updated with the full recovered E1 datastream on the rising edge
of RCLK.
Receive Link Clock. A 4kHz to 20kHz clock (Sa bits) for the RLINK output. See
Section 12 for details.
78
RLINK
79
82
RLCLK
RCLK
Receive Clock. 2.048MHz clock that is used to clock data through the receive side
framer.
Receive Channel Clock. A 256kHz clock that pulses high during the LSB of each
channel. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
92
RCHCLK
Receive Channel Block. A user-programmable output that can be forced high or low
during any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used, such as Fractional E1, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications,
for external per-channel loopback, and for per-channel conditioning. See Section 10 for
details.
1
RCHBLK
Receive Serial Data. Received NRZ serial data. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated on the rising edges of
RSYSCLK when the receive side elastic store is enabled.
95
98
RSER
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which
identifies either frame or CAS/CRC4 multiframe boundaries. If the receive side elastic
store is enabled, then this pin can be enabled to be an input at which a frame or
multiframe boundary pulse synchronous with RSYSCLK is applied.
Receive Frame Sync. An extracted 8kHz pulse, one RCLK wide, is output at this pin
that identifies frame boundaries.
RSYNC
97
96
RFSYNC
RMSYNC
RDATA
Receive Multiframe Sync. An extracted pulse, one RSYSCLK wide, is output at this
pin, which identifies multiframe boundaries. If the receive side elastic store is disabled,
then this output will output multiframe boundaries associated with RCLK.
Receive Data. Updated on the rising edge of RCLK with the data out of the receive side
framer.
85
Receive System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic
100
RSYSCLK store function is enabled. Should be tied low in applications that do not use the elastic
store. Can be burst at rates up to 8.192MHz.
Receive Signaling Output. Outputs signaling bits in a PCM format. Updated on rising
94
99
RSIG
edges of RCLK when the receive side elastic store is disabled. Updated on the rising
edges of RSYSCLK when the receive side elastic store is enabled. See Section 14.
Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is
RLOS/LOTC
12 of 87
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
