DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL POSITION
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be
transmitted).
B1
TDS0M.7
B2
B3
B4
B5
B6
B7
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
TDS0M.1 Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be
transmitted).
B8
TDS0M.0
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
[Repeated here from Section 5 for convenience]
(MSB)
(LSB)
LIRST RESALGN TESALGN
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL POSITION
NAME AND DESCRIPTION
LIRST
CCR5.7
CCR5.6
CCR5.5
Line Interface Reset.
RESALGN
TESALGN
Receive Elastic Store Align.
Transmit Elastic Store Align.
Receive Channel Monitor Bit 4. MSB of a channel decode that
RCM4
CCR5.4
determines in which receive channel the data will appear in the RDS0M
register. See Section 8 for details.
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
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