DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
(MSB)
(LSB)
LIRST
RESA
TESA
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL POSITION
NAME AND DESCRIPTION
Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the clock recovery state machine and jitter
attenuator. Normally this bit is only toggled on power-up. Must be
cleared and set again for a subsequent reset.
LIRST
RESA
CCR5.7
Receive Elastic Store Align. Setting this bit from a zero to a one may
force the receive elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
Should be toggled after RSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 12 for
details.
CCR5.6
Transmit Elastic Store Align. Setting this bit from a zero to a one may
force the transmit elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
Should be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 12 for
details.
TESA
RCM4
CCR5.5
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the RDS0M
register. See Section 8 for details.
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
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