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DS2154LNA2+ 参数 Datasheet PDF下载

DS2154LNA2+图片预览
型号: DS2154LNA2+
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100]
分类和应用: PC电信电信集成电路
文件页数/大小: 124 页 / 982 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers  
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)  
(MSB)  
(LSB)  
TESF  
TESE  
JALT  
RESF  
RESE  
CRCRC  
FASRC  
CASRC  
SYMBOL POSITION  
NAME AND DESCRIPTION  
Transmit-Side Elastic Store Full. Set when the transmit-side elastic  
store buffer fills and a frame is deleted.  
TESF  
RIR.7  
Transmit-Side Elastic Store Empty. Set when the transmit-side elastic  
store buffer empties and a frame is repeated.  
TESE  
RIR.6  
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches  
to within 4–bits of its limit; useful for debugging jitter attenuation  
operation.  
JALT  
RIR.5  
Receive-Side Elastic Store Full. Set when the receive side elastic store  
buffer fills and a frame is deleted.  
RESF  
RESE  
RIR.4  
RIR.3  
RIR.2  
Receive-Side Elastic Store Empty. Set when the receive side elastic store  
buffer empties and a frame is repeated.  
CRC Resync Criteria Met. Set when 915/1000 codewords are received  
in error.  
CRCRC  
FAS Resync Criteria Met Event (FASRC). Set when three consecutive  
FAS words are received in error. Note: During a CRC resync the FAS  
synchronizer is brought online to verify the FAS alignment. If during this  
process a FAS emulator exists, the FAS synchronizer may temporarily  
align to the emulator. The FASRC will go active indicating a search for a  
valid FAS has been activated.  
FASRC  
CASRC  
RIR.1  
RIR.0  
CAS Resync Criteria Met. Set when two consecutive CAS MF  
alignment words are received in error.  
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)  
(MSB)  
(LSB)  
CSC5  
CSC4  
CSC3  
CSC2  
CSC0  
FASSA  
CASSA  
CRC4SA  
SYMBOL POSITION  
NAME AND DESCRIPTION  
CSC5  
CSC4  
CSC3  
CSC2  
SSR.7  
SSR.6  
SSR.5  
SSR.4  
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.  
CRC4 Sync Counter Bit 4.  
CRC4 Sync Counter Bit 3.  
CRC4 Sync Counter Bit 2.  
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB is  
not accessible.  
CSC0  
FASSA  
CASSA  
CRC4SA  
SSR.3  
SSR.2  
SSR.1  
SSR.0  
FAS Sync Active. Set while the synchronizer is searching for alignment  
at the FAS level.  
CAS MF Sync Active. Set while the synchronizer is searching for the  
CAS MF alignment word.  
CRC4 MF Sync Active. Set while the synchronizer is searching for the  
CRC4 MF alignment word.  
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