DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
—
RSRE
THSE
TBCS
RCLA
SYMBOL POSITION
NAME AND DESCRIPTION
Transmit-Side Elastic Store Enable.
0 = elastic store is bypassed
TESE
CCR3.7
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select. See Section 10.1 for
details.
TCBFS
CCR3.6
TIRFS
CCR3.5
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e., Per-
Cannel Loopback function)
-
CCR3.4
CCR3.3
Not Assigned. Should be set to zero when written to.
Receive-Side Signaling Reinsertion Enable. See Section 10.2 for details.
0 = do not reinsert signaling bits into the data stream presented at the
RSER pin
RSRE
1 = reinsert the signaling bits into data stream presented at the RSER pin
Transmit-Side Hardware Signaling Insertion Enable. See Section 10.1
for details.
0 = do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin
THSE
CCR3.2
1 = insert signaling from the TSIG pin into the data stream presented at
the TSER pin
Transmit-Side Backplane Clock Select.
TBCS
RCLA
CCR3.1
CCR3.0
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz/4.096MHz/8.192MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0 = RCL declared upon 255 consecutive zeros (125ꢀs)
1 = RCL declared upon 2048 consecutive zeros (1ms)
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