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DS2154LNA2+ 参数 Datasheet PDF下载

DS2154LNA2+图片预览
型号: DS2154LNA2+
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100]
分类和应用: PC电信电信集成电路
文件页数/大小: 124 页 / 982 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers  
20.2. Nonmultiplexed Bus AC Characteristics  
AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (MUX = 0)  
(VDD = 3.3V M5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V M5%, TA = 0°C to +70°C for DS21554L;  
VDD = 3.3V M5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V M5%, TA = -40LC to +85LC for DS21554LN.)  
(See Figure 20-4 to Figure 20-7.)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
Setup Time for A0 to A7, Valid to  
t1  
0
ns  
CS Active  
Setup Time for CS Active to Either  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RD, WR, or DS Active  
Delay Time from Either RD or DS  
75  
20  
Active to Data Valid  
Hold Time from Either RD, WR, or  
0
DS Inactive to CS Inactive  
Hold Time from CS Inactive to Data  
5
Bus Tri-State  
Wait Time from Either WR or DS  
75  
10  
10  
10  
Active to Latch Data  
Data Setup Time to Either WR or  
DS Inactive  
Data Hold Time from Either WR or  
DS Inactive  
Address Hold from Either WR or DS  
Inactive  
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0)  
ADDRESS VALID  
A0–A7  
D0–D7  
DATA VALID  
5ns MIN/20ns MAX  
t5  
WR  
CS  
RD  
t1  
0ns MIN  
0ns MIN  
t2  
t3  
t4  
0ns MIN  
75ns MAX  
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