DS1621S 参数 Datasheet PDF下载

DS1621

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth-bit.

Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are

defined. The DS1621 works in both modes.

Acknowledge:

Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into account. A master must signal an end of data to the slave

by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Figure 4. DATA TRANSFER ON 2-WIRE SERIAL BUS

Figure 4 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the

R/W bit, two types of data transfer are possible:

1.

Data transfer from a master transmitter to a slave receiver.

The first byte transmitted by the

master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge

bit after each received byte.

2.

Data transfer from a slave transmitter to a master receiver.

The first byte, the slave address, is

transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data

bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the bus will not be released.

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