DS1621
TLF
= Temperature Low Flag. This bit will be set to “1” when the temperature is less than or equal
to the value of TL. It will remain “1” until reset by writing “0” into this location or removing power from
the device. This feature provides a method of determining if the DS1621 has ever been subjected to
temperatures below TL while power has been applied.
NVB = Nonvolatile Memory Busy flag. “1” = Write to an E2 memory cell in progress, “0” =
nonvolatile memory is not busy. A copy to E2 may take up to 10 ms.
POL
= Output Polarity Bit. “1” = active high, “0” = active low. This bit is nonvolatile.
1SHOT = One Shot Mode. If 1SHOT is “1”, the DS1621 will perform one temperature conversion upon
receipt of the Start Convert T protocol. If 1SHOT is “0”, the DS1621 will continuously perform
temperature conversions. This bit is nonvolatile.
X
= Reserved.
For typical thermostat operation the DS1621 will operate in continuous mode. However, for applications
where only one reading is needed at certain times or to conserve power, the one-shot mode may be used.
Note that the thermostat output (TOUT) will remain in the state it was in after the last valid temperature
conversion cycle when operating in one-shot mode.
2-WIRE SERIAL DATA BUS
The DS1621 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master." The devices that are controlled by the master are “slaves." The bus must
be controlled by a master device which generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1621 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (See Figure 4):
CꢀData transfer may be initiated only when the bus is not busy.
CꢀDuring data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
