Monolithic CMOS Analog Multiplexers
LOGIC INPUT
r
t < 20ns
f
3V
50%
0
t < 20ns
+2.4V
+15V
EN
V
S1
S1
0
SWITCH
OUTPUT
0.8V
DG508A
DG509A
ALL S
+5V
V
D
AND DA
(SEE FIG. 1)
TRANSITION
TIME
0.8V
V
S8
S8
SWITCH
OUTPUT
D
A0, A1, (A2)
GND
t
DB, D
V-
transition
S ON
t
S ON
8
V
LOGIC
INPUT
transition
1
1kΩ
50Ω
t
ON
t
OFF
35pF
(EN)
-15V
(EN)
0
SWITCH
OUTPUT
0.1V
0
V
D
Figure 3. Break-Before-Make Test Circuit
(SEE FIG. 2)
(ON) (OFF)
TIME
TENABLE t
t
0.9V
V
0
0
S
V
V
SWITCH
OUTPUT
S
50%
V
D
(SEE FIG. 3)
OPEN TIME
0V
(B.B.M INTERVAL)
t
open
Figure 4. Timing Diagram for Figures 1, 2, and 3
Table 1 b. DG509A Truth Table
Table 1a. DG508A Truth Table
A2
X
0
A1
X
0
A0
X
0
EN
0
ON SWITCH
A1
X
A0
X
EN
0
ON SWITCH
NONE
NONE
1
1
2
3
4
5
6
7
8
0
0
1
1
2
3
4
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
X = Don’t care.
1
0
1
1
1
1
0
1
1
1
1
1
X = Don’t care.
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7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
