78M6610+LMU Data Sheet
Register Locations
Use Word addresses for I2C and SPI interfaces and Byte addresses for the SSI (UART) protocol.
Nonvolatile (NV) register defaults are indicated with a ‘Y’. All other registers are initialized as described in
the Functional Description.
Word Byte
Addr Addr
Register
Type NV Description
0
1
0
COMMAND
FWDATE
INT
INT
Y
Command Register (see Command Register section)
Firmware release date in hex format (0x00YMDD)
Status bit mask for MP0 pin
3
2
6
MASK0
INT
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
3
4
5
6
7
8
9
A
B
C
D
E
9
C
F
MASK4
MASK6
MASK7
MASK10
INT
INT
INT
INT
INT
INT
INT
S.21
S.21
S.21
S.21
S.21
S.21
S.23
S.23
S.23
S.23
S.10
S.10
S.23
S.23
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
Status bit mask for MP4 pin
Status bit mask for MP6 pin
Status bit mask for MP7 pin
Status bit mask for MP10 pin
12
15
18
1B
1E
21
24
27
2A
2D
30
33
36
39
3C
3F
42
45
48
4B
4E
51
54
57
5A
5D
60
63
66
69
6C
6F
72
75
78
STICKY
Status bits to hold until cleared by host
High-Rate Samples per Low Rate (default 400)
Number of Calibration Cycles to Average
Phase compensation (+/-4 samples) for S1 input
Phase compensation (+/- 4 samples) for S3 input
Input S1 Gain Calibration. Positive values only
Input S0 Gain Calibration. Positive values only
Input S3 Gain Calibration. Positive values only
Input S2 Gain Calibration. Positive values only
Input S0 Offset Calibration
SAMPLES
CALCYCS
PHASECOMP1
PHASECOMP3
S1_GAIN
S0_GAIN
S3_GAIN
S2_GAIN
S1_OFFS
S0_OFFS
S3_OFFS
S2_OFFS
T_GAIN
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
Input S1 Offset Calibration
Input S3 Offset Calibration
Input S2 Offset Calibration
Temperature Slope Calibration
T_OFFS
Temperature Offset Calibration
HPF_COEF_I
HPF_COEF_V
VSURG_INT
VSAG_INT
STATUS
STATUS_SET
STATUS_RESET
DIO_STATE
CYCLE
FRAME
FRAME
DIVISOR
HARM
DEVADDR
CONTROL
CONFIG
VTARGET
VSURG_VAL
VSAG_VAL
Current Input HPF Coefficient. Positive values only
Voltage Input HPF Coefficient. Positive values only
Voltage Surge Detect Interval
Voltage Sag Detect Interval
Alarm and Device Status Bits
Used to Set Status bits
Used to Reset Status bits
State of DIO pins
High-Rate Sample Counter
48 bit Low-Rate Sample Number – Low word
48 bit Low-Rate Sample Number – High word
Actual samples in previous low-rate period
Harmonic Selector, default: 1 (fundamental)
High order address bits for I2C and UART interfaces
Control (see text)
Input Source M (gain) selectors and more
Voltage Calibration Target. Positive values only
Voltage Surge Threshold. Positive values only
Voltage Sag Threshold. Positive values only
Y
INT
Y
Y
Y
Y
S.23
S.23
S.23
45
Rev 0
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
